Technologies and services

• Enabling STCO design and simplifying design for chiplet-based solutions
• Providing CTR platforms and technologies for the whole supply chain
• Developing advanced organic substrate architectures, enabling panel-level fabrication, heterogeneous integration, and improved functionality and reliability
• Meeting rising electronics demands through leading wafer-level packaging (WLP) R&D

Electronic packaging and assembly connect tiny integrated circuits (ICs) to printed circuit boards (PCBs), enabling the creation of complex microelectronic systems. As device performance and functionality increase, innovations in packaging are becoming critical. The lines between semiconductor design, packaging, and system engineering are blurring—requiring closer collaboration across all areas.

Packaging not only protects the IC but also influences product size, performance, reliability, and thermal management. Advanced packaging technologies like Surface Mount Technology (SMT), Flip Chip, Wafer Level Packaging (WLP), and 3D integration using Through Silicon Vias (TSVs) are enabling smaller, faster, and more efficient systems.

WLP, especially in its fan-in (FI-WLP) and fan-out (FO-WLP) forms, supports ultra-thin devices like smartphones, wearables, and medical electronics. New methods like chip-first embedding, which eliminate traditional wire bonding or flip-chip techniques, offer high-frequency performance advantages with significantly reduced inductance and capacitance.

Overall, packaging is evolving into a key enabler for next-generation electronics through heterogeneous integration and system-level innovation.