CTR platform

Characterization, test, reliability and failure analysis, security analysis

Services

© Fraunhofer ENAS
  • Comprehensive characterization, test and reliability platform to support manufacturing
  • Provision of complete functional and reliability test capabilities and strategies along the whole value chain
  • Innovative and unique test system (photonics test head)
  • Test service (volume test)
  • Knowledge transfer (test hardware and methods)
  • Support by cutting-edge failure analysis capabilities for industrial technology ramp up, series production and market introduction
  • Support of continuous market success by field by counterfeit detection and identification of IP violations

Characterization

© Fraunhofer ENAS

Target

  • Advanced characterization tools and methods for chiplets and QMI systems with large variety of signal types (DC, RF, high speed digital, mm-wave, optical)
  • High accurate and low-noise measurement capabilities for determination and evaluation of heterointegrated devices
  • Methods to characterize dielectric materials in sub-THz frequencies
  • Identification of technology  weaknesses and validation of design and simulation models of chiplets, modules and systems

Innovations

  • Characterization of high-speed transmitter and detector chiplets
  • Efficient electrical characterization tools (high accurate, low noise)
  • Electro-optical characterization of QMI systems with backend optics
  • Antenna and RF component characterization from mm-wave to THz
  • Characterization of high-performance optical interconnects

Impact

  • Reliable information about the performance of technologies and components at the development stage ensure
  • Short development cycles and direct feed back to STCO to optimize the design
  • Specification handbook for processes, chiplets, systems
  • Demonstrator functionality

Test

© Fraunhofer ENAS

Target

  • Facilities for wafer-level and chip-level testing for optical, RF, and mm-wave signals, …80 Volt, … 18 GHz in the clean room
  • High accurate and low-noise measurement capabilities for determination and evaluation of heterointegrated devices
  • Testhead for wafer level and chip level optical and RF/mm-wave tests
  • Efficient methods for volume test to ensure statistically relevant feedback to technology development and for the pilot fabrication series

Innovations

  • Test for MRAM-based chiplets, e.g. on interposers and of critical high-speed communication IP and chiplets before assembly
  • Burn-in test of chiplets
  • Electro-optical test (position, warp, scratches,..) and X-ray inspection as part of the fabrication pilot line
  • Test of systems for S-parameters up to 250 GHz under load-pull in D band (110 -170 GHz).

Impact

  • Fabrication yield of 2.5/3D stacks not influenced by faulty chiplets
  • Innovative test system for RF/photonics as USP
  • Provision of service for external partners
  • Knowledge transfer to external partners

Reliability and failure analysis

© Fraunhofer IMWS

Target

  • Provision of reliability testing and failure analysis capabilities for chiplets & HI
  • Understanding of technology and application related defect risks and identification of new failure modes and degradation mechanisms
  • Consideration of quality and reliability aspects during development -> improved design for reliability
  • Assurance of manufacturing quality and stable long-term behavior of chiplets & HI devices

Innovations

  • Test methods to assess and mitigate discharging risks
  • Non-destructive 3D defect analysis and electrical fault isolation
  • Multi-domain reliability testing and failure analysis techniques
  • Advanced material characterization and FEM- and AI-based degradation and lifetime modeling
  • New concepts for Design for Reliability

Impact

  • Cutting-edge characterization and failure capabilities for defect analysis & quality control for:
  • Accelerating device development & qualification
  • Optimizing manufacturing yield
  • Improving reliability under harsh environments
  • Supporting faster market introduction

Security analysis

© Fraunhofer AISEC

Target

  • Implementation of architecture-level security measures and security IP blocks on chiplet, HI device up to system level
  • Establishing of strong framework to ensure hardware security along the manufacturing chain
  • Characterization and improvement of device and system resilience against physical attacks 

Innovations

  • Improved resilience against hardware attacks of complex HI devices and systems
  • Improved trustworthiness along the supply chain including OSATs
  • Improved application related reliability of security features

Impact

  • Advanced techniques for security assessment of security relevant models in heterogeneous systems.
  • Test and analysis for authenticity check and counterfeit defense
  • Test and analysis for IP-protection
  • Test and analysis for legacy products for long-living systems