Design

Target

• Simplifying the design process of chiplet-based systems by provision of foundational chiplet building blocks & methods for chiplet selection
• Provision of IPs and chiplets that cover analog, RF, compute & AI, Interfacing, power management, opto, MEMS in (Bi)CMOS and III-V processes
• Enablement of System Technology Co-Optimization (STCO) design of chiplet-based systems by provision of models for IPs and chiplets
• Validation in demonstrator systems: HPC, Sensing, Photonics, RF

Innovations

• Consistent representation by model – IP – chiplet
• DfX on IP & chiplet level:
• Design for Manufacturing (DfM), Design for Reliability (DfR), Design for Security (DfS), Design for Test (DfT)
• Initiation of an ecosystem for chip IP components by establishing systematics and design capabilities:
  making IPs and dies “chiplet-ready”

Impact

• Building links to the European design platform, to make “From Lab to Fab“ in the field of heterogeneous integration easier and more accessible for EU companies to use new technologies and functionalities
• Contributions to IP and chiplet standards

Target

• Systematic design flows for both quasi-monolithic and 2.5/3D integration
• Extensive simulation capabilities to handle and manage complexity across electrical, thermal, mechanical, and process integration aspects
• Provision of P/ADKs and process module descriptions to enable package design with high densities, RF, heat sinks, multi-material chiplets, etc.
• Extension proposals of interface standards towards DfT, analog, and power

Innovations

• STCO design flow that provides all necessary data formats, PDKs, ADKs, interfaces, tools for IPs & packages for various scenarios
• Cost-effective design for sensing, photonics, RF with high reuse
• Advanced performance design for HPC/AI, sensing, photonics (very low pitches, very low high line/space, very high line count, very high throughput)

Impact

• Powerful integration and design infrastructure for
  applications like:
  • advanced sensing, advanced photonics, HPC
  • cost-effective sensing, photonics and RF
• Enablement of early and fast evaluation of system variants with co-optimization of cost, yield, performance, supply

• A System Technology Co-Optimization (STCO) ecosystem
  • Access to new pilot line functionalities
  • Enablement of advanced system integration
  • Cost/Benefit analysis
  • Standardisation of integration technologies
  • Large design space that covers
    • analog, RF, compute & AI, interfacing, power mgmt., opto, MEMS in (Bi)CMOS and III-V processes
    • both quasi-monolithic and 2.5/3D integration
• A holistic system design approach to enable fully integrated
  systems and access the new technologies
• Enablement of radically new products even in medium quantities with high yields and at attractive costs