News and press releases

Silvaco Group, Inc. (Nasdaq: SVCO) (“Silvaco” or the “Company”), a provider of TCAD, EDA software, and SIP solutions that enable innovative semiconductor design and digital twin modeling through AI software and automation, today announced a strategic R&D collaboration with Fraunhofer Institute for Silicon Technology (ISIT). The partnership aims to accelerate development of next-generation Gallium Nitride (GaN) devices using Silvaco’s industry-leading Power Devices Solution to perform Design Technology Co-Optimization (DTCO). This collaboration aligns with Fraunhofer ISIT’s role in the EU Chips Act initiative through its participation in the APECS pilot line.

Efficient failure analysis is essential for high-performance electronic applications and the development of cutting-edge solutions for the European semiconductor industry. This was the conclusion of the CAM workshop at the Fraunhofer Institute for Microstructure of Materials and Systems IMWS in Halle (Saale) yesterday. More than 150 international guests learned about possible applications for gallium nitride (GaN) and the pilot line for Advanced Packaging and Integration for Electronic Components and Systems (APECS).

A consortium of 12 European partners has been selected in the framework of the European Chips Act to develop the EU Chips Design Platform. This cloud-based platform will facilitate access to advanced semiconductor design infrastructure, training, and capital for fabless semiconductor start-ups, small and medium enterprises and research organizations. With the EU Chips Design Platform, coordinated by imec, an important new resource is being put in place to support technological development and industrial competitiveness across Europe. The German partners are the Fraunhofer institutes and the Leibniz IHP cooperating in the Research Fab Microelectronics Germany (FMD).

On March 31, 2025, at the Hannover Messe, the Research Fab Microelectronics Germany (Forschungsfabrik Mikroelektronik Deutschland FMD) officially unveiled its new Chiplet Application Hub. Designed to serve as a central platform for the development and application of chiplet technologies, the hub aims to bridge the gap between research and industrial use. By working closely with industry partners, the hub accelerates the development of chiplets made in Germany, elevating industrial research to a new level. At the national level, it complements FMD’s role in the Chips for Europe Initiative, further reinforcing Germany’s technological resilience. The hub's research, development, and prototyping activities build on the infrastructure of the APECS pilot line, ensuring direct pathways to industrial application.

The European Chips Act of 2022 calls for European microelectronics pilot lines to develop and validate novel design and fabrication technologies for next-generation microelectronic chips. Fundamental for new electronic components and systems, advanced packaging and heterogeneous integration technologies are the focus of the APECS pilot line. An article in »Nature Reviews Electrical Engineering« from Patrick R. Bressler, Michael Töpper & Peter Ramm.

On Dec. 17, 2024, the Research Fab Microelectronics Germany (FMD) announced that the pilot line for advanced packaging and heterogeneous integration for electronic components and systems (APECS) has started operations. The main objective is to help researchers develop and test new heterogeneous integration methods, particularly emerging chiplet technologies. To find out more about APECS and how it contributes to the European ecosystem, Pat Brans from EE Times Europe spoke to Stephan Guttowski, managing director of FMD.

In this exclusive interview, Pat Brans from EE Times Europe spoke with Stephan Guttowski, managing director of Research Fab Microelectronics Germany (FMD), about the announcement this morning of a new pilot line, called APECS, an acronym for Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems. APECS is designed to improve microelectronic system production in Europe and is supported by the EU Chips Act. It is a collaborative effort involving experts from institutions such as CEA-Leti and imec. In this video, Guttowski explained how the initiative will leverage existing capabilities at FMD and enhance access to state-of-the-art technologies for companies across Europe.

The pilot line for “Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems” (APECS) marks a major leap forward in strengthening Europe’s semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union´s goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the “Chips for Europe” initiative. The overall funding for APECS amounts to € 730 million over 4.5 years.

As executive director of the Fraunhofer Institute for Integrated Circuits (IIS) and chairman of the Research Fab Microelectronics Germany (FMD), Albert Heuberger sits at the forefront of applied research in Germany. Fraunhofer IIS is one of the 13 institutes that make up FMD. Each contributes expertise and infrastructure to develop new technologies and techniques ready for industrial use. Pat Brans from EE Times Europe caught up with Heuberger to discuss semiconductor packaging and heterogeneous system integration technologies that improve the computing power and energy efficiency of electronic systems.