Chiplet integration platform

• 2.5 and 3D stack HD integration of heterogeneous devices for silicon and non-silicon devices with µTSVs in the sub-µm range using microbumps and hybrid bonding innovations
• MEMS and Sensor Integration with 3D stacked chiplets up to 300 mm wafers for highly functional modules
• Scale-up of process implementation using embedding technologies into advanced substrates up to 600mm
• Module and subsystem integration HPC, NGC, Power-E, Sensors, UWBG & RF/Opto from chiplet to substrate
• Scale-up of process implementation for high-end chiplet architectures (3D, 2.5D) up to 600 mm
• Open Access for other Pilot Lines, RTO´s and industry to facilitate early adoption of new technologies & fast-track innovations

Target

• Anorganic Interposers for advanced CMOS on 300mm
• Multi-Functional Interposers for RF, Optoelectronics & MEMS*
• Passive Functionalities in Interposer
• Organic HD Interposers
• Providing all required technologies for interposers based chiplet integration

Innovations

• Sub-micron TSV´s, AR20:1,UHD Routing – incl. PostCMOS
• Glass, HR-Si, Ceramics with TxV´s and resp. routing, on 200mm
• IPDs, integrated cooling, LWGs, structural features
• Advanced HD substrates (5µm L/S)
• Laminates with embedded IC
• Panel Scale Interposers using FO processes

Impact

• Preparation for UHD Wafer Scale Integration, supporting QMI and Advanced Packaging
• Interposers serving Multi-Domain Systems (MEMS, Opto, RF, Sensing, *) for broad range of functionalities
• Critical functionalities integrated in a single process flow
• Module- and System Interfaces towards the applications

Target

• 3D Stacking of advanced CMOS wafers and non-CMOS
  heterogenous/multimaterial wafers
• 2.5D Integration of chiplets onto interposer
• Preparation for chiplet interfaces
• Specific technologies for MEMS and sensor chiplets
• Providing all technologies to realize heterogeneously integrated modules

Innovations

• High density Wafer2Wafer stacking with sub µm precision using hybrid bonding
• Stack-integration of specific functionalities for HIS providing hermeticity, capping
• Die2Wafer integration for heterogenous functionalities
• Chiplet interface adaption with RDLs, terminal metal & bumps

Impact

• Chiplet based module realization with functionalities from different domains
• Highest density integration of heterogenous chiplets
• Enabling STCO methodology throughout domains

Target

• System scale assembly for Heterosystems with Modules and Subsystems
• Quality and Reliability assured functionalities at system level
• Novel integration concepts for 3D volumetric systems

Innovations

• High density, high speed, assembly on advanced substrates
• Reliable assembly for multi-layered heterogenous systems (L1-L3)
• Embedded and fan out integration of systems
• Hybrid integration concept using embedding and fan out on panel scale
• Layer-by-Layer stacking for 3D volumetric system integration

Impact

• Functional highly integrated systems for novel applications like AI, autonomous mobility,
• RF and Communication, Sensors, Power and Photonics
• Supporting STCO methodology from L1-L3