Development and validation of complex, integrated RF systems up to 325 GHz through four coordinated sub-demonstrators covering mobile communication, wireless links, and radar applications. Focus lies on heterogeneous integration of III–V, SiGe/BiCMOS and FDSOI CMOS technologies and the validation of the APECS design enablement (PDKs, ADKs, tools), including testing and pilot-line verification.
Heterogeneous integration of RF chiplets across multiple semiconductor platforms using interposers, flex substrates, and fan-out wafer level packaging (FOWLP). Enables compact, scalable mm-wave and sub-THz modules with improved efficiency, bandwidth, and system-level performance for radar, sensing and communication applications.
Four complementary sub-demonstrators:
1) InP-on-BiCMOS 6G D-band transceiver (110–170 GHz)
2) Sub-THz (256 GHz) BiCMOS–mHEMT radar front-end
3) 3Flex D-band radar system
4) D-band communication module
System-Technology Co-Optimization (STCO) is applied to optimize system performance across technologies.
The demonstrator validates heterogeneous integration for high-performance RF systems and demonstrates pilot-line readiness for mm-wave and sub-THz modules. It enables scalable solutions for 5G/6G communication, sensing, and radar applications, including deployment on flexible and non-planar surfaces.